Typically an electronic circuit comprises a plurality of different sub-circuits which may be responsible for performing different functions. For example, an integrated circuit is typically constructed of a plurality of individual circuit elements. In such circuitry it is often a requirement to propagate a common signal to the different circuit elements which make up to a particular electronic circuit.
In the world of digital circuit design, designers are often required to create multi-clock designs or multi-domain clock designs. Multi clock implies that a design has at least two clocks, but possibly many more clocks, that are asynchronous. Furthermore the digital designs will include at least one, although possibly multiple signals, across the boundaries between the clock environments. If the signals are not synchronised then the circuit will develop errors.
Systems are known for controlling the transfer of a signal, which is propagated from a first circuit element in a first clocking domain, to a second circuit element in a second clocking domain, and wherein the first and second clocking domains are asynchronous. In the past, one way of handling the asynchronous clock domains was by the timing the signal clock into the second clock again, and ensuring the rate of change and the pulse width is acceptable between the domains. However this approach relies on knowing the rate and pulse width so is typically is only used for regular timing reference signals. A further way of handling asynchronous clock domains in the past was by using software to update a register held in each specific clock domain where in the registers being accessible via an asynchronous bridge.
If one were to consider for example an integrated circuit having a plurality of circuit elements, each of which having their own clock, and each having to act on a common signal, then it will be appreciated that it is necessary to adequately test or verify the synchronization of these circuit elements such that the integrated circuit as a whole when manufactured or realized will not develop any errors.
The testing and verification of the system on chip designs are further complicated by the various permutations of the asynchronous clock boundaries. It would not be practical to generate tests for each boundary where the arrival of either clock edge could be undefined. This is because it would typically require repeating a potentially long test with clock domains programmed at varying relative frequencies and phases to highlight potential design flaws in request-grant and valid-ACK type asynchronous handover schemes.
It is known that in some verification environment configurations a rule based hardware description language (HDL) verification or property checking can be implemented. However these rule based verifications do not pick up on design errors in all situations as the intention of the function is not always well defined to the tool.